1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacture thereof, and more particularly, to a technique to readily form a three-dimensional structure of the device.
2. Description of the Prior Art
In semiconductor devices used in semiconductor integrated circuits or the like, the way of forming a desired circuit is usually such that impurities like ions are first implanted into the surface of a silicon substrate, and then diffused to form the device. The devices thus obtained are generally formed only on the surface of the silicon substrate, arranged in the lateral direction (lateral device). As a result, a current conducting region is limited to the surface area of the silicon substrate, allowing the resulting circuit to have a low efficiency in device forming and wiring. In order to solve this problem, a way of forming devices in the vertical direction (vertical device) has been proposed. This method is to form devices at a right angle to the surface of the substrate, thus obtaining a high efficiency in device forming and wiring.
FIG. 1 shows a method for manufacturing a conventional vertical PNP type transistor. According to this method, impurities are first implanted into a P type silicon substrate 75 through an oxide layer 79. The implanted ions are then diffused to form an N.sup.30 type separation layer 81 which acts as buried layer for use in device separation (FIG. 1A).
The N.sup.+ type separation layer 81 is next subjected to impurities implantation, and thereafter heated at a high temperature. This heat treatment allows the implanted ions to be diffused to form a P.sup.+ type buried layer 77 on the N.sup.+ type separation layer 81, whereas an N.sup.31 type epitaxially grown layer 4 is grown on the P type silicon substrate 75. Thus, the P.sup.30 type buried layer 77 acting as collector layer is provided between the P type silicon substrate 75 and the N.sup.- type epitaxially grown layer 4.
Further, by means of photoetching method (photoresist), a P.sup.+ type diffusion layer 82, an emitter layer (P.sup.30 type) 84 and an N.sup.+ type diffusion layer 86 are formed in the N.sup.- type epitaxially grown layer 4. Thereafter, a collector electrode 83, an emitter electrode 85 and a base electrode 87 are attached to the P.sup.30 type diffusion layer 82, the emitter layer (P.sup.30 type) 84 and the N.sup.+ type diffusion layer 86, respectively.
By these processes, the PNP type transistor having the P.sup.+ type buried layer 77, the N.sup.- type epitaxially grown layer 4 and the emitter layer (P.sup.+ type) 84 is obtained. In this transistor, each device is arranged in the vertical direction so as to stand at a right angle (FIG. 1C, arrow 90) to the surface of the substrate, thus formed as a three-dimensional structure. This structure allows an efficient circuit.
The conventional semiconductor device, however, has the following disadvantages. The N.sup.+ type separation layer 81 and the P.sup.+ type buried layer 77 are lain between the P type silicon substrate 75 and the N.sup.- type epitaxially grown layer 4, as shown in FIG. 1C. In order to construct this structure, the N.sup.+ type separation layer 81 and the P.sup.+ type buried layer 77 are first formed, and thereafter the N.sup.- type epitaxially grown layer 4 are grown on the P type silicon substrate 75. The epitaxial growth at this step usually requires heating at 1000.degree. C. or more. The heat treatment, however, is responsible for the following problem. Namely, impurities, contained in the N.sup.+ type separation layer 81 and the P.sup.+ type buried layer 77, are again made to diffuse and redistribute by the heat treatment. The effect of redistribution is such that it changes electrical characteristics of the transistor. Also, it increases the device size. Accordingly, a fine-tuned control is necessary to obtain the transistor of which circuit elements are constructed in three dimensions, having desired electrical characteristics.